Bengaluru (on-site, hours flexible)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
We are seeking a highly experienced Principal Engineer – SoC Architect to define and drive next-generation SoC architectures for high-performance semiconductor products. This role requires deep expertise in system-level architecture, high-speed I/O integration, performance optimization, scalability, and cross-functional technical leadership.
The ideal candidate will play a critical role in shaping SoC platforms from concept through silicon realization, with strong emphasis on high-speed interfaces, subsystem architecture, interoperability, power/performance optimization, and architectural innovation.
SoC Architecture Definition
Define end-to-end SoC architecture for complex semiconductor platforms across compute, memory, interconnect, security, and peripheral subsystems.
Drive architectural tradeoff analysis involving performance, power, area (PPA), latency, scalability, and cost.
Collaborate with product, software, firmware, RTL, verification, physical design, and validation teams throughout the development lifecycle.
High-Speed I/O Architecture
Lead architecture and integration of high-speed interfaces including: Drive system-level performance modeling and interface optimization.
System Performance & Modeling
Drive power-aware architecture decisions and dynamic performance management strategies.




Lead technical reviews, design evaluations, and architecture signoff discussions.
Drive alignment across hardware, firmware, software, and platform ecosystems.
Design and verification teams on implementation feasibility, Firmware/software teams on boot, drivers, and runtime optimization, Validation teams on bring-up and debug strategies and Product and business teams on roadmap alignment.
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field.

- 12+ years of experience in SoC/system architecture and semiconductor product development.
- Proven expertise in large-scale SoC architecture definition and subsystem integration.
- Solid understanding of High-speed I/O architectures and protocols, On-chip interconnects and coherency fabrics, Memory subsystem architecture, Performance modeling and analysis and Power/performance optimization techniques.
- Experience with architecture modeling tools, simulation environments, and performance analysis methodologies.
- Deep expertise in one or more high-speed I/O technologies such as PCIe Gen5/Gen6, CXL, UCIe, HBM, or advanced SerDes architectures.

Experience with heterogeneous compute architectures involving CPU, GPU, AI/ML accelerators, or DSP subsystems.
Knowledge of chiplet-based architectures and advanced packaging technologies.
Experience with silicon bring-up, post-silicon debug, and system validation.
Familiarity with automotive, AI/ML, datacenter, networking, or mobile SoC platforms.
Publications, patents, or industry contributions in SoC or high-speed interconnect architecture are a plus.
Influence long-term SoC technology and platform strategy.
Drive innovation in scalable and reusable architecture frameworks.
Champion engineering excellence, design quality, and execution rigor.
Foster collaboration across globally distributed engineering organizations.

📌 Principal Engineering Architect (Bengaluru)
🏢 Ayar Labs
📍 Bengaluru