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Job Description

Job Description
Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features Develop verification environments using System Verilog and UVM Architect and develop scalable and re-usable test benches, using the framework of the verification methodology Develop BFMs / Checkers / monitors / Scoreboards Build pseudo-random tests to verify and get full Functional coverage Debug Regression failures in RTL and Gatelevel simulations, analyze Functional Coverage gaps and improve tests to cover the gaps Document verification strategy including Test plans, Testbench, Random tests, etc.

Requirements:




Bachelor’s or Master’s degree in electrical engineering or related degree with 8+ years relevant experience Proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Valuable command of Object-Oriented Programming principles Knowledge of Host interface protocols such as PCIe, SAS, SATA is desired Knowledge of AMBA AXI/AHB/APB protocols Experience writing Functional Coverage, pseudo random tests Flexible to work in any IP/Subsystem/SoC projects Capability to work independently and deliver Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

📌 ASIC Verification Engineer (Pune)
🏢 Broadcom
📍 Pune