30 Oct
|
Source right
|
Bengaluru
30 Oct
Source right
Bengaluru
Position: Senior Verification Engineer, DDR PHY (IRT60ST RM 4494) Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY. Must-have
• DDR PHY architecture, DFI protocol, JEDEC standards (latest gens)
• LPDDR5/LPDDR4 hands-on experience
• Verilog/SystemVerilog, UVM/OVM
• Solid debug and root-cause skills, including SS/SoC/post-silicon issues Good To Have
• Perl scripting
• Post-silicon bring-up, HW-SW debug
• AHB/AXI protocol knowledge
📌 Senior Verification Engineer, DDR PHY (Bengaluru)
🏢 Source right
📍 Bengaluru