Seeking a highly experienced Physical Design Engineer with deep hands-on expertise in full-chip implementation, sign-off STA, and PPA optimization for complex ASIC/SoC designs. The role requires architectural ownership, strong technical judgment, and expertise in driving design closure.
Key Responsibilities
- Own full-chip physical implementation from floorplanning to routing and sign-off.
- Drive STA, timing budgeting, and timing closure across MMMC scenarios.
- Lead implementation and optimization using Cadence Innovus.
- Resolve complex setup/hold violations, congestion, signal integrity, and clocking challenges.
- Drive PPA optimization, ECOs, and synthesis-to-route timing correlation.
- Define physical design methodologies and implementation strategies for advanced SoC designs.
Required Technical Skills
- Strong hands-on expertise in full-chip Physical Design and sign-off STA.
- Proficiency in Cadence Innovus and Synopsys PrimeTime / Cadence Tempus.
- Expertise in floorplanning, placement, CTS, routing, and timing closure.
- Strong knowledge of MMMC, SDC, OCV/AOCV/POCV, SI, and parasitic analysis.
- Tcl scripting and physical design flow automation.
Candidate Profile
- 12–16 years of relevant ASIC/SoC Physical Design experience.
- Solid architectural problem-solving and technical ownership.
- Proven experience driving complex full-chip implementation and tapeout closure.
- Hands-on technical leadership; not a people-management-focused role.