RTL Design Engineer (Synthesis & Timing Closure)
Experience Required: 5+ years
Location: Hyderabad, India
Key Skills: Synthesis, SDC Timing Constraints, Timing Closure, CDC/RDC, Lint (SpyGlass), and DFT signoff.
Tools: Design Compiler / Fusion Compiler, SpyGlass, CDC0in, GCA, and TCL scripting.
Interested candidates can share their updated resume directly to
[email protected].
📌 Senior RTL Design Engineers (Hyderabad)
🏢 ACL Digital
📍 Hyderabad