Company Description NovaRays Semi is a world-class analog and mixed-signal design company delivering turnkey, silicon-proven IP across SerDes, UCIe, die-to-die connectivity, memory interfaces, sensor front ends, power management, and high-performance custom circuits. The team brings over 100 years of combined experience in mixed-signal IP delivery, including architecture, circuit design, AMS verification, physical design, process migration, and silicon bring-up. NovaRays Semi follows a precision-driven engineering philosophy focused on predictable execution, uncompromising quality, and aggressive PPA optimization. Its solutions support demanding markets such as AI and cloud compute, hyperscale data centers, automotive safety, robotics and IoT, networking, and next-generation client/server platforms.

Role Description: We are looking for a DFT Engineer to own scan and ATPG for our IP programs, with a primary focus on UCIe and PCIe. You will improve test coverage, generate patterns,



and work closely with the physical design and STA teams to close timing and ECO issues.

Key Responsibilities:
Improve ATPG scan coverage
Generate test vectors and patterns
Run gate-level simulations (GLS) with SDF back-annotation
Work with the PD and STA teams to resolve timing issues and give feedback on ECOs
Review and edit scan DEF and SDC constraints when ECO changes require it
Support scan stitching and insertion in the physical design flow

Required skills:
Scan and ATPG background
ATPG coverage analysis and improvement
Vector and pattern generation
GLS simulation with SDF
Scan DEF and SDC constraint review and editing
Working with PD and STA teams on timing and ECO closure

Valuable to have:
PD scan stitching and insertion experience (an advantage)
Experience with UCIe or PCIe IP (primary IP focus, but not mandatory)

📌 Dft Engineer Bengaluru
🏢 NovaRays Semi
📍 Bengaluru