The RTL Technical Lead will own the technical execution of one or more digital IP blocks, working closely with architecture, verification, PD, STA and DFT teams. The engineer should be capable of defining micro-architecture, reviewing RTL quality, mentoring junior engineers, and ensuring timely delivery.
Responsibilities
Understand architecture and system specifications.
Develop micro-architecture for assigned IP blocks.
Partition work among RTL engineers.
Own RTL delivery for assigned subsystem.
Review RTL coding quality.
Conduct design reviews and code reviews.
Drive closure of
Lint
CDC
RDC
Synthesis issues
Timing-related RTL issues
Work with Verification team for bug closure.
Coordinate with PD, STA and DFT teams.
Support silicon bring-up and debug.
Mentor junior RTL engineers.
Participate in customer technical discussions.
Required Skills
8+ years RTL Design experience
Expert in Verilog/System Verilog
Robust micro-architecture skills
Block and subsystem level RTL ownership
FSM, Pipelines, FIFOs, Memory Interfaces
Clock gating
Reset architecture
CDC/RDC methodologies
Lint closure
Timing-aware RTL coding
Synthesis concepts
STA fundamentals
Experience with Synopsys/Cadence RTL tool flow
Valuable debugging capability
Excellent communication skills