Job Description:

As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.

Key Responsibilities:

- Work closely with the ATE engineer on yield improvement and analysis.
- Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
- Participate in block and chip-level DFT implementation, developing and executing all related tasks.
- Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
- Perform ATPG and pattern simulation for both MBIST and scan.
- Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
- Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.

Required Qualifications:





- Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience
- Required experience in silicon bring-up and yield improvement.
- Solid understanding of DFT techniques.
- Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
- Experience in MBIST architecture and insertion.
- Experience in analyzing and debugging simulation failures.
- Solid understanding of digital logic fundamentals.
- Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
- Proficiency with Perl or other scripting languages.
- Solid communication and interpersonal skills.
- Plus: Experience in STA constraint development in DFT modes

R027594

📌 DFT Engineer (Bengaluru)
🏢 Broadcom
📍 Bengaluru