"Candidates with 2 to 5 years experience is mandatory
Experience in RTL coding using Verilog/SV
Experience in design using Xilinx or Altera devices
Experience in using Vivado or Quartus
Key Responsibilities
Experience in supporting lab debug
Good understanding of FPGA debugging techniques
Skill Requirements
2 to 5 years experience in front end design
Experience in CDC/Linting/Tool Flow
Experience with ASIC/SoC development flow including synthesis/Timing Constraints development is preferred
Must Have Skill
RTL Design
Positive to Have Skill
Other Requirements
Experience in RTL Synthesis
Scripting experience is preferable"
📌 Senior Designer (India)
🏢 HCLTech
📍 India
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