Senior RTL Design Engineers (Secunderabad)

Senior RTL Design Engineers (Secunderabad)

31 Oct
|
Alten Calsoft Labs
|
Secunderabad

31 Oct

Alten Calsoft Labs

Secunderabad

RTL Design Engineer (Synthesis & Timing Closure)

Experience Required: 5+ years

Location: Hyderabad, India

Key Skills: Synthesis, SDC Timing Constraints, Timing Closure, CDC/RDC, Lint (SpyGlass), and DFT signoff.

Tools: Design Compiler / Fusion Compiler, SpyGlass, CDC0in, GCA, and TCL scripting.

Interested candidates can share their updated resume directly to [HIDDEN TEXT].

📌 Senior RTL Design Engineers (Secunderabad)
🏢 Alten Calsoft Labs
📍 Secunderabad

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