Job Summary
Own microarchitecture, RTL development and integration for PCIe, ASP and MMC subsystems
Key Responsibilities
Develop synthesizable Verilog/SystemVerilog RTL.
Design/integrate PCIe, processor interfaces, DMA/GDMA, interrupts, NoC, telemetry and control logic.
Drive lint, CDC/RDC, synthesis, LEC and timing readiness.
Debug RTL/DV integration issues and support RTL Freeze/ECO closure.
Skill Requirements
Robust Verilog/SystemVerilog and digital design fundamentals.
PCIe/high-speed interface and AXI/AHB/APB experience.
Hands-on experience with CDC/RDC, lint, synthesis, STA and LEC.
Exposure to SpyGlass, Design Compiler/Genus, PrimeTime and Verdi.
Must Have Skill
RTL Design,RTL integration
Good to Have Skill
Other Requirements
📌 Senior Design Lead (India)
🏢 HCLTech
📍 India