Senior Verification Engineer

Experience: 5+ Years
Locations: Hyderabad / Bangalore / Pune / Bhubaneswar / Ahmedabad

Role:
We are looking for a Senior Verification Engineer with strong experience in ASIC/SoC/IP Design Verification.

Key Responsibilities:
Develop and execute verification plans and testbenches.
Develop SystemVerilog/UVM-based settings, sequences, assertions, and coverage.
Perform functional, regression, and protocol-level verification.
Debug RTL and simulation failures and drive coverage closure.
Collaborate with Design, Architecture, and Validation teams.

Required Skills:
Solid SystemVerilog & UVM experience.
ASIC/SoC/IP Design Verification experience.
Hands-on with VCS/Xcelium/Questa.
Positive knowledge of SVA, Functional & Code Coverage.
Scripting experience in Python/Perl/TCL.
Experience with protocols such as PCIe, DDR, UFS, AXI, USB, Ethernet, or MIPI is preferred.

Qualification: B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Electrical, or related field.

📌 Senior Asic Verification Engineer Pune
🏢 Scaledge
📍 Pune