Job Summary

We are seeking a Senior IP Design engineer with significant hands-on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debug.

Key Skills
Hands-on experience in FPGA RTL design, logic verification, debug and timing closure
Programming skills (e.g.: C/C++, Perl, TCL or Python)
Experience in high-speed IO protocols (e.g.: PCIe, Ethernet, CPRI, JESD204B/C)
Experience in hardware validation and debug is a plus
Experience in soft IP packaging, example design and testbench development will be an added advantage

Education and General
BS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of FPGA system design experience.
Independent and self-motivated, capable of executing under agile setting and uncertainties

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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