For more Details, connect with me on LinkedIn: Kartheek Guntuku

Role: Senior / Lead Physical Design Engineer (RTL to GDSII)

Location: Hyderabad & Bangalore

Experience: 6 to 9 Years

Notice: Immediate to 20 Days

Role Overview: We are looking for an experienced Senior / Lead Physical Design Engineer (6 to 9 Years) to handle complete Netlist-to-GDSII implementation and signoff on advanced technology nodes (5nm and 3nm) using Synopsys and Siemens EDA tool flows.

Key Responsibilities:
RTL to GDSII Flow & Implementation:
Execute complete physical design flow including Synthesis, Placement, and Routing (P&R;) using Synopsys Fusion Compiler.
Perform Block-level and SoC-level Floorplanning, power mesh structuring, and pin planning.
Implement and optimize Clock Tree Synthesis (CTS) for low skew, latency, and agile power.
Define and manage design constraints (SDC) across timing, power, area, and design rules to optimize overall PPA (Power, Performance, Area).
Signoff & Physical Verification:




Carry out full-chip and block-level Static Timing Analysis (STA) and timing signoff using Synopsys PrimeTime.
Perform accurate parasitic extraction using StarRC.
Drive power integrity, static/energetic IR-drop, and EM analysis closure using Ansys Redhawk-SC.
Execute comprehensive Physical Verification including DRC, LVS, Antenna, and Density closure using Siemens Calibre on advanced 5nm/3nm process nodes.
ECO Implementation & Automation:
Implement functional and logical ECOs using Formality ECO.
Drive timing ECO generation and closure using Prime Closure.
Develop and enhance Tcl/Perl/Python scripts for automated flow execution and reporting.

Requirements:
6 to 9 years of relevant Physical Design experience.
Robust hands-on expertise in Synopsys Fusion Compiler and PrimeTime.
Proven track record on sub-7nm/FinFET process nodes (5nm / 3nm).
Immediate to 15 days joiners preferred.

📌 Lead / Senior Physical Design Engineer Hyderabad
🏢 Softpath Technologies
📍 Hyderabad