We are looking for an experienced Memory Layout Engineer to work on the physical design and delivery of advanced memory IPs, including SRAM and Register Files, at advanced technology nodes.

Key Responsibilities
Perform end-to-end memory layout design and floor planning for advanced technology nodes.
Design and integrate bitcells, peripheral circuits, decoders, sense amplifiers, and memory arrays.
Optimize layouts for PPA, routing efficiency, power integrity, and EM/IR reliability.
Deliver DRC-, LVS-, and DFM-clean GDS along with complete IP collateral.
Collaborate with circuit design, CAD, verification, and SoC integration teams.
Drive layout improvements to achieve high-density and performance targets.
Support memory compiler development and customer-specific customizations.
Ensure compliance with foundry design rules and reliability requirements.

Required Skills & Qualifications




Hands-on experience in Memory Layout design.
Solid expertise in Cadence Virtuoso and Calibre verification tools.
Positive understanding of memory architectures, including SRAM, ROM, DRAM, and CAM.
Knowledge of design rules, parasitic effects, and physical verification flows.
Exposure to layout automation and scripting using SKILL, TCL, or Python is an advantage.
Robust debugging and problem-solving skills in routing, EM/IR, and DRC challenges.
Ability to collaborate effectively with cross-functional teams.
Mentoring experience is an added advantage.

Preferred Candidate Profile

Candidates with hands-on experience in memory layout design, advanced-node technologies, and physical verification are encouraged to apply.

📌 Memory Layout Engineer Noida
🏢 Exiger Technologies
📍 Noida