Lead RTL Design and Design Verification teams across PCIe, ASP and MMC subsystem development.
Key Responsibilities
Own technical execution, schedules, milestones, resources, risks and dependencies.
Lead RTL/DV planning, reviews, integration, regression/coverage closure and sign-off.
Drive technical issue resolution and cross-functional coordination.
Track program health and provide transparent stakeholder/customer updates.
Coordinate Architecture, RTL, DV, PD, DFT, Firmware, Emulation and Validation teams.
Skill Requirements
Robust ASIC/SoC development and technical leadership experience.
Good understanding of RTL, SystemVerilog/UVM, PCIe, AXI, DMA and NoC.
Experience driving RTL/DV programs through RTL Freeze and DV sign-off.
Strong planning, risk management, technical problem-solving and stakeholder communication.
Must Have Skill
RTL integration,UVM
Good to Have Skill
Other Requirements
📌 Senior Technical Architect (India)
🏢 HCLTech
📍 India
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