Senior Designer (India)

Senior Designer (India)

01 Nov
|
HCLTech
|
India

01 Nov

HCLTech

India

Job Summary

We are seeking a motivated Junior FPGA Design Engineer with a strong foundation in FPGA design and an interest in high-speed networking and embedded systems. The ideal candidate will contribute to the development, integration, verification, and debugging of FPGA-based solutions for next-generation networking platforms.

The candidate will work closely with senior FPGA architects and engineering teams in developing packet-processing pipelines, Ethernet interfaces, PCIe subsystems, and FPGA-based acceleration solutions.

Key Responsibilities

FPGA Design & Development

- Develop and maintain RTL modules using Verilog/SystemVerilog.
- Support implementation of FPGA-based networking and packet-processing functions.
- Participate in the design and integration of:
- - Ethernet interfaces
- PCIe subsystems
- DMA data paths
- Packet parsers
- Queue management modules
- Statistics and monitoring blocks

- Assist in FPGA bring-up and board-level validation activities.

Skill Requirements

- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
- 4 to 6 years of FPGA design and development experience.
- Good understanding of Verilog/SystemVerilog and digital design fundamentals.




- Experience with FPGA development tools such as:
- - AMD Vivado
- Intel Quartus (optional)

- understanding of FPGA implementation flow:
- - Synthesis
- Place and Route
- Timing Analysis
- Timing Closure

- Knowledge of embedded systems and FPGA-based system integration.

Understanding of standard communication protocols and interfaces

Must Have Skill

FPGA Design

Positive to Have Skill

Other Requirements

FPGA & Digital Design

- RTL Design
- FSM Design
- Clocking and Reset Design
- CDC Basics
- FPGA Debug Techniques
- Memory Interfaces (BRAM, DDR basics)

Interfaces & Protocols

- AXI4
- AXI-Stream
- UART
- SPI
- I2C

Networking Fundamentals

- Ethernet
- VLAN
- IPv4 / IPv6
- TCP / UDP
- Basic packet processing concepts

Preferred Qualifications

- Exposure to AMD Versal, Zynq UltraScale+, or UltraScale+ FPGA devices.
- Basic understanding of PCIe architecture.
- Exposure to DMA engines and high-speed interfaces.
- Familiarity with networking concepts such as:
- - RSS
- VLAN
- MPLS
- VXLAN

- Experience with simulation tools such as:
- - QuestaSim
- ModelSim
- XSIM

- Knowledge of Python, TCL, or scripting for automation.

📌 Senior Designer (India)
🏢 HCLTech
📍 India

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