Job Summary

Job Description — Emulation Engineer
Experience: 4–8 Years
Domain: ASIC/IP Emulation & Pre-Silicon Validation
Platform: Synopsys ZeBu
Role Overview
We are looking for hands-on Emulation Engineers to perform pre-silicon validation of complex Design IP using the Synopsys ZeBu emulation platform.
The engineer will work on emulation bring-up, test development, regression, functional and performance validation, and debug of Design IP such as PCIe, DDR, Ethernet, MIPI CSI/DSI and other high-speed interfaces.
The role requires strong RTL/verification fundamentals, debugging ability and hands-on exposure to hardware emulation.
Key Responsibilities

- Compile and bring up complex Design IP RTL on Synopsys ZeBu.
- Configure clocks, resets, interfaces, transactors and emulation IP.
- Support RTL compilation, partitioning, mapping and runtime setup.
- Develop and maintain IP-level emulation environments.
- Integrate ZeBu transactors and protocol solutions.
- Develop and execute - Functional tests, Protocol tests, Corner-case tests, Error-injection tests, Stress tests, Performance/bandwidth tests
- Validate IPs including – PCIe, DDR/LPDDR, Ethernet, MIPI CSI/DSI, Other high-speed connectivity IP
- Adapt simulation-based verification environments for emulation.
- Develop automated regression and results-analysis scripts.
- Debug RTL, protocol, testbench, transactor and ZeBu runtime failures.
- Analyze waveforms, logs and transaction-level traces for root-cause identification.
- Reproduce failures and work with RTL/verification engineers to resolve issues.
- Track test results, defects and verification closure metrics.
- Document environment setup, test procedures, results and known limitations.

Required Technical Skills





- 4–8 years of experience in ASIC/SoC design verification, emulation or prototyping.
- Hands-on experience with Synopsys ZeBu or a comparable hardware emulation platform is strongly preferred.
- Strong knowledge of Verilog/SystemVerilog.
- Good understanding of UVM and IP-level verification methodology.
- Experience with at least one major interface/protocol:

o PCIe
o DDR/LPDDR
o Ethernet
o MIPI CSI/DSI

- Knowledge of AXI/AHB/APB is desirable.
- Good RTL and waveform debugging skills.
- Understanding of transactor-based acceleration/emulation.
- Experience integrating protocol VIP or emulation transactors is desirable.
- Scripting/automation experience using Python, Perl, Tcl, shell or equivalent.
- Familiarity with tools such as VCS, Verdi and ZeBu.
- C/C++ knowledge for software-driven validation is an advantage.

Key Competencies
The candidate should demonstrate:

- Strong analytical and debugging skills.
- Ability to understand Design IP specifications and derive test scenarios.
- Ability to independently debug failures across RTL, verification and emulation environments.
- Positive understanding of verification methodology and corner-case testing.
- Strong ownership of assigned technical deliverables.
- Ability to work effectively with Design, Verification and Emulation teams.
- Clear technical communication and documentation skills.
- Ability to learn new protocols and emulation technologies quickly.

Education
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI/Microelectronics, Computer Science or equivalent.

Key Responsibilities

Emulation

Skill Requirements

Must Have Skill

Emulation

Good to Have Skill

Other Requirements

📌 Senior Design Lead (India)
🏢 HCLTech
📍 India