Purpose Designs the 64-way interleaved 7-bit SAR ADC array. Responsibilities
· Sub-ADC design: 1-3 GS/s, ENOB at least 6 bit, power and area.
· Mismatch, skew (about 50 fs) and offset analysis with calibration support.
· Reference and decoupling network design. Required SAR ADC design; time-interleaving errors and calibration; Monte Carlo; low-power design. Preferred 100 GS/s+ ADC experience. Common requirements
· Works from the budget workbook and the ES-id electrical specification; changes to a number go through change request.
· Writes the design document for their block (docs 01 to 11), including honest status: planned, simulated or measured.
· Explicit written English, version control, issue tracking.
· Typical background: BS or MS in electrical or computer engineering (PhD for algorithm and PLL/ADC research roles).