- Design Verification Engineer responsible for developing testbenches using SystemVerilog and UVM to verify complex digital designs.
- Collaborate with cross-functional teams to identify requirements and develop verification plans, test cases, and debug issues.
- Develop high-quality reusable code components such as functions, macros, and sequences to accelerate verification closure.
- Analyze results from simulations runs to identify defects in the design. Job
Requirements:
- 5-15 years of experience in SOC Verification with expertise in PCIe protocol.
- Robust understanding of SystemVerilog language and its application in DV environment.
- Experience with UVM (Universal Verification Methodology) is required; knowledge of other HVLs like VHDL or Verilog is a plus.