Job Title: Senior DO-254 FPGA Design Engineer

Location: [Bengaluru]

Department: Avionics Hardware & Embedded Systems Engineering

Experience Level: Mid-to-Senior (5+ Years)

Role Overview

We are seeking an experienced DO-254 FPGA Design Engineer to lead the architecture, RTL design, and certification of safety-critical FPGAs for next-generation airborne Multi-Function Displays (MFDs) and real-time avionics video processing systems. In this role, you will develop high-bandwidth, low-latency video pipelines—including ARINC 818, sensor fusion overlays, and graphics compositing—while ensuring full compliance with RTCA DO-254 (DAL A/B) objectives from conceptual planning through Final Stage of Involvement (SOI-4) audits.

Key Responsibilities

FPGA Architecture & Video Pipeline Design

- Architect and implement real-time video processing blocks in VHDL or Verilog, including frame buffers, scalers, de-interlacers, alpha blenders, color space converters, and symbology overlays.
- Design and integrate high-speed avionics video and data interfaces such as ARINC 818 (ADVB), SMPTE SDI, DisplayPort, DVI/HDMI, LVDS, and PCIe.
- Implement high-throughput memory controllers (DDR4/DDR5, QDR) and on-chip bus fabrics (AXI4, Avalon) to sustain deterministic multi-stream video routing with zero frame drops.
- Perform synthesis, place-and-route, Static Timing Analysis (STA), and Clock Domain Crossing (CDC) analysis across multiple asynchronous video and system clocks.

DO-254 Compliance & Certification Lifecycle
- Author and maintain DO-254 certification lifecycle data, including the Plan for Hardware Aspects of Certification (PHAC), Hardware Design Plan (HDP), and Hardware Requirements Standards.
- Capture, decompose, and trace high-level system requirements to detailed Hardware Requirements Documents (HRD) and conceptual/detailed design descriptions using IBM DOORS or Jama Connect.




- Enforce strict RTL coding standards (e.g., CNES, STARC) and execute automated rule-checking and lint flows to guarantee deterministic, synthesis-safe hardware behavior.
- Support FAA/EASA/CEMILAC DER or certification authority audits across SOI-1 through SOI-4 milestones, resolving formal review action items and managing Problem Reports (PRs).

Hardware Integration & Target Testing
- Bring up and validate FPGA designs on target avionics MFD hardware using high-speed oscilloscopes, protocol analyzers, video pattern generators, and on-chip debug tools (ChipScope/Vivado ILA, SignalTap).
- Collaborate with verification engineers to close structural coverage metrics (Statement, Branch, Condition, FEC/Toggle) required for DAL A/B elemental analysis.
- Work closely with embedded software teams developing DO-178C graphics drivers (OpenGL SC, ARINC 661) and PCB hardware engineers to optimize signal integrity, power budgets, and thermal performance.

Required Qualifications

- Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, Computer Engineering, or a related field.
- FPGA Design Experience: 5+ years of hands-on RTL design experience in VHDL (preferred for DO-254) or Verilog targeting AMD/Xilinx (Zynq UltraScale+ MPSoC, Kintex-7/UltraScale) or Microchip/Microsemi (PolarFire, SmartFusion2) devices.
- DO-254 Expertise: Proven track record taking at least one airborne electronic hardware project through full RTCA DO-254 / EUROCAE ED-80 (DAL A or DAL B)



lifecycle milestones (SOI-1 to SOI-4).
- Video & Display Processing: Strong practical knowledge of digital video timing, pixel processing pipelines, frame synchronization, and cockpit display interface protocols (ARINC 818, LVDS, SDI, or DisplayPort).
- EDA Toolchains: Proficiency with AMD Vivado, Microchip Libero SoC, or Intel Quartus Prime, alongside simulation and analysis tools such as QuestaSim/ModelSim, Questa CDC, and ReqTracer.
- Requirements & Configuration Management: Hands-on experience establishing bidirectional traceability in DOORS, Jama, or Polarion, and managing baselines via Git, SVN, or ClearCase.

Preferred Qualifications

- Direct experience implementing ARINC 818 transmitter/receiver IP cores, fiber-optic SerDes transceivers, and ARINC 661 cockpit display system architectures.
- Familiarity with safety assessment processes (SAE ARP4754A, ARP4761), including FMEA, FMES, and Single Event Upset (SEU) mitigation techniques (TMR, ECC, scrubbing).
- Experience with SoC-based heterogeneous architectures (e.g., Zynq UltraScale+ MPSoC) partitioning safety-critical video pipelines in programmable logic alongside DO-178C processor subsystems.
- Working understanding of SystemVerilog/UVM verification environments and hardware-in-the-loop (HIL) automated test benches.

What We Offer

- Opportunity to architect mission-critical cockpit display technology deployed on next-generation commercial and defense aircraft.
- Competitive base salary, performance bonuses, and comprehensive health and retirement advantages.
- Access to state-of-the-art avionics integration labs, optical display test benches, and ongoing DER certification training.

Please send updated resume to [email protected]

#Hiring #Aerospace #DO254 #FPGA #VHDL #Verilog #RTLDesign #HardwareEngineering #EmbeddedSystems #Avionics

📌 Avionics:FPGA Design Engineer (Bengaluru)
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