Job Summary

Role Summary

Exp - 7 to 18 yrs

Standard Cell Characterization Architect/Manager to Lead a project and work on end-to-end standard cell library development. The role involves schematic design, characterization, view generation, and supporting automation across design flows with a strong focus on performance, power, and quality.

Key Responsibilities

Key Responsibilities

- Provide technical leadership to a project and be responsible for overall delivery.
- Develop standard cell libraries, including:
- - Schematic design for basic gates, combinational and sequential cells

- Perform SPICE simulations (pre- and post-layout) and analyze design metrics
- Optimize designs for performance, power, and area (PPA)
- Review layouts and ensure alignment with schematic and design intent
- Ensure quality and accuracy of characterization deliverables
- Collaborate with layout, verification, and characterization teams

Skill Requirements

Required Skills (Must-Have)

- Should be able to provide Technical Leadership for a project.
- Should be able to setup flow from scratch and mentor team members
- Strong understanding of CMOS and FinFET device characteristics, challenges, and constraints
- Strong knowledge of CMOS digital circuit design (combinational & sequential circuits)




- Deep understanding of timing parameters:
- - Delay, pin capacitance, setup/hold, recovery/removal, MPW

- Good knowledge of power parameters:
- - Static power, dynamic power, leakage, capacitance

- Hands-on expertise in:
- - SPICE simulations and measurement of design parameters
- Post-layout simulation

- Strong understanding of:
- - PVT variations and device impact on performance
- Digital circuit optimization for better PPA

- Experience in schematic and extracted netlist simulations
- Ability to review layouts and correlate with design intent
- Knowledge of reliability analysis in FinFET / advanced nodes

Basic scripting skills in Linux / Perl / Python

Must Have Skill

STD-Cell Circuit Design

Good to Have Skill

Other Requirements

Desired Skills (Good-to-Have)

- Understanding of deep submicron process effects
- Hands-on experience with advanced nodes ( 16nm)
- Experience with EDA tools:
- - Cadence (Spectre, Virtuoso), waveform viewers

- Good knowledge of complex standard cell circuits
- Strong communication and teamwork skills
- Positive attitude, adaptability, and willingness to learn
- Detail-oriented, versatile, and proactive approach

📌 Technical Architect (India)
🏢 HCLTech
📍 India