SoC-level verification using SystemVerilog and UVM
Key Responsibilities
- Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
- Writing and debugging constraint-random tests
- Development and analysis of functional coverage and code coverage
Skill Requirements
- TVP processor experience.
- experience in CPU integration verification or C‑based / assembly‑based testing.
- Hands on exposure to Python scripting;
- Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
- Writing and debugging constraint-random tests
- Development and analysis of functional coverage and code coverage
- Solid Debugging Skills
Must Have Skill
SystemVerilog,UVM
Good to Have Skill
Other Requirements
📌 Senior Design Lead (India)
🏢 HCLTech
📍 India
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.