Design and execute verification for PCIe, ASP and MMC subsystems at IP/subsystem/SoC level
Key Responsibilities
Develop SystemVerilog/UVM verification environments, test plans, sequences, scoreboards, assertions and coverage.
Verify PCIe, processor integration, DMA/GDMA, interrupts, NoC, telemetry, queues and CSR/control logic.
Execute regressions, debug failures and drive functional/code/assertion coverage closure.
Work with RTL, Architecture, Firmware and Emulation teams through DV sign-off.
Skill Requirements
Strong SystemVerilog, UVM, SVA and functional coverage.
PCIe, preferably Gen5/Gen6, and AXI/AHB/APB knowledge.
IP/subsystem/SoC verification and debug experience.
VCS/Xcelium/Questa, Verdi and Python/Perl/Tcl/Shell.
Must Have Skill
UVM
Positive to Have Skill
Other Requirements
📌 Senior Design Lead (India)
🏢 HCLTech
📍 India
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