Director – Design Verification (SoC / ASIC) Leadership + Technical Strategy

Location:
Bangalore

Experience:
18–25+ years Role level: Director / Senior Director / Head of Design Verification

Job description
Role overview We are looking for an experienced Design Verification Director to lead large-scale ASIC and SoC verification programmes. The candidate will be responsible for verification strategy, technical execution, organisation development, customer engagement and delivery excellence across multiple IP, subsystem and full-chip verification teams.

Key responsibilities
1. Verification leadership: Lead multiple teams covering IP, subsystem, SoC and full-chip verification. 2. Technical ownership: Define verification methodologies, strategies, sign-off criteria and quality standards. 3. SoC verification: Drive complex SoC-level verification involving CPU, GPU, PCIe, DDR, USB, Ethernet, NoC and other high-speed interfaces. 4. Methodology: Establish and drive SystemVerilog, UVM, constrained-random verification, assertions and functional coverage. 5. Execution management: Own project planning, resource allocation, schedules, milestones and delivery commitments. 6. Customer management: Engage with semiconductor customers, architects, engineering directors and senior stakeholders. 7. Business leadership: Support pre-sales, proposals, effort estimation,



technical presentations and account growth. 8. People management: Build and mentor senior managers, verification managers, architects and technical leads. 9. Quality and sign-off: Drive coverage closure, regression efficiency, bug management and verification sign-off. 10. Organisation growth: Develop technical capabilities, hiring strategy, succession planning and verification excellence. Required technical expertise
- SystemVerilog, UVM, OVM
- IP, subsystem and full-chip SoC verification
- Functional coverage, code coverage and assertion-based verification
- AXI, AHB, APB, ACE, CHI
- PCIe, DDR, HBM, CXL, USB, Ethernet and UCIe
- ARM / RISC-V CPU subsystem verification
- Formal verification and low-power verification
- Emulation: Palladium, Veloce, Zebu
- Simulation: VCS, Questa, Xcelium Candidate profile – ideal background Target candidates who have:
- 20+ years of semiconductor/VLSI experience.
- 5–10+ years leading large DV organisations.
- Managed 50–100+ engineers across multiple projects or teams (preferred, not mandatory).
- Experience delivering multiple complex SoCs through tapeout.
- Worked with semiconductor product companies or large VLSI service organisations.
- Managed customer engagements, technical delivery and business growth.

📌 Verification - Director (India)
🏢 smartsoc solutions
📍 India