Company Description Rakiya Information Technology Solution Pvt Ltd is a specialized services company focused on ASIC, FPGA, SoC, and embedded systems design and verification, including analog and mixed-signal verification. With strong domain expertise in networking and telecom, the organization supports complex, high-performance semiconductor projects. The team is described as one of the best in the industry, with a culture that values technical excellence and collaboration. Quality and meticulous execution are the highest priorities, and Rakiya is committed to delivering best-in-class solutions to its clients. This environment offers professionals the opportunity to work on challenging projects and grow their skills in advanced chip design. Role Description This is a full-time, on-site role based in Chennai, focused on Analog Layout Design, Physical Design, and Design Verification. Day-to-day responsibilities include creating and optimizing analog and mixed-signal layout for ASICs and SoCs, performing physical design implementation, and ensuring compliance with design rules and foundry requirements. The role involves running layout versus schematic (LVS), design rule checks (DRC), and other sign-off verification flows to ensure design integrity and manufacturability. The professional in this role will collaborate closely with circuit designers, verification engineers, and system architects to meet performance, power, and area goals.



Additional tasks may include documentation of design processes, participation in design reviews, and continuous improvement of layout and verification methodologies. Qualifications
• Analog and digital Layout Design skills related to IC/ASIC design, with solid understanding of physical design concepts.
• Graphics and Graphic Design skills for creating clear technical diagrams and visual documentation when needed.
• Page Layout experience for preparing technical reports, design documentation, and presentation materials.
• Digital Marketing knowledge to support internal or external technical communication and branding efforts when relevant.
• Hands-on experience with EDA tools for analog layout, physical design, and verification (e.g., Cadence Virtuoso, Synopsys, Mentor tools).
• Solid understanding of semiconductor device physics, analog circuits, and mixed-signal design fundamentals.
• Proficiency in sign-off verification flows, including DRC, LVS, and parasitic extraction, and familiarity with foundry process technologies.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a closely related field.
• Ability to work on-site in Chennai, collaborate effectively in cross-functional teams, and communicate clearly in written and spoken English.
• Prior experience in networking or telecom-related chip design projects is an advantage.

📌 Analog Layout Design, Physical Design, Design Verification (Chennai)
🏢 RAKIYA Information Technology Solution
📍 Chennai