## Job highlights
- RTL,prototyping and acceleration on FPGA from DSP datapaths to multi-FPGA ASIC prototypes. . Job Details.
Job Type
Full time.
- Full time. . What experience is expected. 3 10 years
- A r sum and a cover letter are both required the cover letter is not optional. . Bring us the difficult part. Tell us the specification,the constraint and the deadline RTL, prototyping and acceleration on FPGA from DSP datapaths to multi-FPGA ASIC prototypes. ### Job Details
Job Type
Full time
Location:
Bengaluru, India ### What the role involves
- Design and implement RTL on FPGA: DSP, high-speed interfaces and datapaths.
- Close timing across the device; partition designs across multi-FPGA prototype boards.
- Bring up boards and validate against the specification at speed. Key
skills:
- FPGA
- RTL
- Timing closure
- SystemVerilog
- Vivado / Quartus
- DSP ### To Apply A CV is fine. What helps more is a paragraph about a problem you solved that was harder than it looked, and what you would do differently now.
Apply through our application form attach your r sum and write a cover letter. The cover letter is required. ### Common Questions #### Where is this role based Bengaluru, India. Full time. #### What experience is expected 3 10 years. The range is a guide rather than a filter make the case if you are outside it. #### How do I apply Apply through the application form. A r sum and a cover letter are both required the cover letter is not optional. ### Bring us the difficult part Tell us the specification, the constraint and the deadline. Programmes that cross silicon, radio, embedded and AI are where Faststream is strongest. Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.