The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.
The Person
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites and time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Key Responsibilities
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements
Preferred Experience
- IP level ASIC verification
- debugging firmware and RTL code using simulation tools
- Verilog, SystemVerilog, C, and C++
- UVM testbenches and Linux/Windows environment
- Scripting language experience: Perl, Ruby, Makefile, shell preferred
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Valuable working knowledge of SystemC and TLM with some related experience
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