Senior Physical Design Engineer (5+ Years)

Role Overview

As a Senior Physical Design Engineer, you will own block/top-level execution from netlist to GDSII, meeting aggressive PPA (Power, Performance, Area) targets on advanced technology nodes.

Education Requirements

- Degree: B.E. / B.Tech / M.E. / M.Tech in Electronics Engineering, Electrical Engineering, VLSI, or Computer Engineering. (Master's degree preferred)

Key Responsibilities

- Drive floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing.
- Analyze and optimize timing, power (static and agile), and area across multiple operational modes and corners.
- Execute Congestion, IR drop, and crosstalk reduction strategies during layout implementation.
- Work with Synthesis, STA, DFT, and Package design teams to resolve integration issues.




- Lead block closure and support top-level chip integration and tape-out activities.

Technical Qualifications

- Experience: 5+ years of hands-on experience in block and top-level Physical Design.
- Tools: High proficiency in Synopsys Innovus / ICC2, Cadence Innovus, or RedHawk.
- Nodes: Proven track record of successful tape-outs on 7nm, 5nm, or lower process nodes.
- Skills: Deep understanding of CTS architectures, high-speed layout techniques, multi-corner multi-mode (MCMM) optimization, and low-power design techniques (UPF/CPF).
- Scripting: Excellent scripting skills in TCL/Python.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru