Hi All, Greetings from HCL Tech. We are Hiring: RTL Design/Integration Lead (Chip Top-Level). Locations: Bengaluru, Noida, Chennai & Hyderabad. ? Experience Min 10+ years in RTL Integration Lead (Chip Top-Level). Proven experience in: Chip-level RTL Integration Ownership Multiple SoC tape outs. ? Role Overview: Lead and own SoC RTL integration for complex chips, ensuring seamless assembly of multiple IPs/subsystems into a functionally correct, synthesis-ready top-level design. This role is central to aligning architecture, design, verification, and physical teams for successful tape out. ?

Key Responsibilities
? RTL Integration Ownership Own top-level RTL integration of SoC: Integrate multiple IPs, subsystems, and third-party blocks Ensure clean connectivity, hierarchy, and modular structure Deliver synthesis-ready, lint-clean, and CDC-clean RTL ? Architecture Alignment Work closely with architecture teams to: Translate SoC architecture into RTL structure Ensure correct implementation of: Interconnects (NoC / bus-based) Address maps Reset and clock architecture ? Interface & Connectivity Management Define and validate: IP interfaces and protocols (AXI, AHB, APB, etc.) Address decoding and interconnect connectivity Resolve: Interface mismatches Integration conflicts across teams ? Clock, Reset & Power Integration Define and integrate: Clocking architecture (multiple clock domains) Reset strategies (global/local resets) Power domains (UPF/CPF alignment) Ensure: Clean CDC/RDC implementation Proper low-power intent integration ? Quality & Signoff Readiness Drive RTL quality checks: Lint (SpyGlass, Lint tools) CDC/RDC analysis Basic synthesis checks Ensure RTL is: DV-ready DFT-ready PD-friendly ? Collaboration Across Teams Interface with:



IP/RTL design teams DV teams (for testbench integration support) DFT teams (for scan/test readiness) PD/STA teams (for implementation alignment) Act as central integration point across all domains ? Debug & Issue Resolution Lead debug of: Integration bugs Boot-up and reset sequence issues Connectivity and functional mismatches Support system-level bring-up in simulation/emulation ? Automation & Flow Development Develop scripts/tools for: RTL stitching Connectivity checks Build and regression flows Improve integration efficiency and repeatability ? Leadership Lead and mentor RTL integration engineers Drive integration schedules, milestones, and reviews Act as owner of top-level RTL quality and readiness ? Required Skills & Expertise ? Technical Strong expertise in: Verilog/SystemVerilog RTL design SoC integration and architecture Deep understanding of: Bus protocols (AXI/AHB/APB) Clock/reset domain design Low-power design (UPF/CPF basics) Experience with: Lint, CDC/RDC tools Synthesis awareness ? Tools Lint: SpyGlass / Questa Lint CDC: SpyGlass CDC / Questa CDC Synthesis: Design Compiler / Genus (Basic Awareness) Version control: Git/Perforce ? Soft Skills Solid system-level thinking Excellent coordination across large teams Problem-solving and debugging mindset ? Good to Have Experience in: NoC-based SoC architectures Emulation/FPGA bring-up Firmware/boot flow understanding Scripting: Python / TCL / Perl ? Success Metrics Clean, integration-ready RTL (lint/CDC clean) Smooth handoff to DV, DFT, and PD teams Minimal integration bugs at system level Predictable integration schedules First-pass success in SoC bring-up Interested Engineers ping me or send invitation to connect further. Email I'd: [email protected] Mobile: +91 (phone hidden).

📌 RTL Design Integration Lead (Bengaluru)
🏢 HCLTech
📍 Bengaluru