Role: ASIC RTL Design Engineer

Mandatory Skill : (RTL Design, RTL Coding & Integration, IP Design, targeted for SOC, Micro architecture, Static checks, ARM Cortex-M7 (CM7), Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)

Experience : 4 Years 22 Years

Notice : Immediate 60 days

Work Location : Bangalore / Hyderabad

- Expertise in SoC subsystem/IP design

- Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

- In depth knowledge on RTL quality checks (Lint, CDC)

- Knowledge of synthesis and low power is a plus

- Positive understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

- Good understanding of timing concepts

- Knowledge of one or more of the interface protocols

a. PCIe
b. DDR
c. Ethernet
d. I2C,



UART, SPI

- Expertise in setting up and using tools like

a. Spyglass Lint/CDC
b. Synopsys DC
c. Verdi/Xcellium

- Understanding of scripting languages like Make flow, Perl ,shell, python etc

- Understanding of processor architecture and/or ARM debug architecture is a plus

- Able to help and debug issues for multiple subsystems

- Able to create/review design documents for multiple subsystems

- Able to support physical design, verification, DFT and SW teams on design queries and reviews

📌 ASIC RTL (Hyderabad)
🏢 Cyberidentitysolutions
📍 Hyderabad