The focus of this role is to plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout.
Responsibilities
Plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout.
Requirements
You have a passion for up-to-date, complex processor architecture, digital design, and implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have solid analytical and problem-solving skills and are willing to learn and ready to take on problems.
Preferred Experience
7+ years of experience in relevant domain.
Experienced with Blocklevel and Toplevel Physical implementation.
Positive understanding and hands-on experience in Lower node technologies. (5nm or below)
Preferably working on Lowpower or processor designs.
Proficient in Working with various EDA tools. Innovus, Fusion compiler, PrimeTime.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
Exposure to leadership or mentorship is an asset
Academic Credentials
Bachelors or Masters degree in computer engineering/Electrical Engineering
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