Role: DV Engineer

Locations: Hyderabad, Ahmedabad, Bangalore.

No. of positions: Multiple

Experience: 3+ years

Requirements

Strond Knowledge of System Verilog and UVM Proven Expertise in Architecting Complex Verification Environments using System Verilog and UVM Ability to quickly ramp-up on complex FPGA Interfaces and must have completed at least one full verification life cycle

Robust Digital and verification Fundamentals

Ability to Understand the specifications and must have experience developing BFMs/UVCs for industry standard protocols

Ability to Analyze Functional and Code reports and experience with the verification closure

Solid Written and verbal Communication Robust knowledge of Verilog/VHDL and must be able to read and understand the complex HDL Coding

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Dv Engineer Ahmedabad
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