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Job Description
Role Purpose
The purpose of the role is to design and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction.
Physical Design Architect
PD Architect
Experience
15 years
Location
Bangalore Hyderabad Kochi Chennai Pune
Domain
ASIC / SoC Turnkey Silicon
Employment
Full time
The Role
Define physical implementation strategy for complex SoCs owning floorplan PPA timing closure and signoff through tape-out.
What You Will Do
- Define physical design strategy: partitioning floorplan power grid clocking and hierarchical flow.
- Own PPA timing power and congestion closure at block and full-chip level.
- Drive signoff: STA IR/EM physical verification formal equivalence and ECO closure.
- Give early feasibility feedback to RTL and architecture teams on timing power and area.
- Co-ordinate with foundry package and DFT teams for a clean tape-out.
- Mentor PD teams; set methodology and automation best practices.
What You Bring
- 15 years in physical design with multiple tape-outs including full-chip or hierarchical implementation.
- Hands-on with advanced FinFET nodes.
- Expert in P&R; tools (Fusion Compiler / ICC2 or Innovus) and signoff tools (PrimeTime Redhawk / Voltus Calibre / ICV).
- Deep expertise in clock tree design low-power implementation (UPF) and timing closure.
- Proven ECO execution and tape-out ownership.
- Tcl / Python automation skills.
Good to Have
- 2.5D / 3D and chiplet physical design
- Package co-design and die-to-die interfaces
- High-frequency multi-GHz designs
Physical Design Architect
PD Architect
Experience
15 years
Location
Bangalore Hyderabad Kochi Chennai Pune
Domain
ASIC / SoC Turnkey Silicon
Employment
Full-time
The Role
Define physical implementation strategy for complex SoCs owning floorplan PPA timing closure and signoff through tape-out.
What You Will Do
- Define physical design strategy: partitioning floorplan power grid clocking and hierarchical flow.
- Own PPA timing power and congestion closure at block and full-chip level.
- Drive signoff: STA IR/EM physical verification formal equivalence and ECO closure.
- Give early feasibility feedback to RTL and architecture teams on timing power and area.
- Co-ordinate with foundry package and DFT teams for a clean tape-out.
- Mentor PD teams; set methodology and automation best practices.
What You Bring
- 15 years in physical design with multiple tape-outs including full-chip or hierarchical implementation.
- Hands-on with advanced FinFET nodes.
- Expert in P&R; tools (Fusion Compiler / ICC2 or Innovus) and signoff tools (PrimeTime Redhawk / Voltus Calibre / ICV).
- Deep expertise in clock tree design low-power implementation (UPF) and timing closure.
- Proven ECO execution and tape-out ownership.
- Tcl / Python automation skills.
Good to Have
- 2.5D / 3D and chiplet physical design
- Package co-design and die-to-die interfaces
- High-frequency multi-GHz designs
Deliver
No.Performance ParameterMeasure
1.Product design engineering and implementationCSAT quality of design/ architecture FTR delivery as per cost quality and timeline POC review and standards
2.Capability development% trainings and certifications completed mentor technical teams Thought leadership content developed (white papers Wipro PoVs)
Mandatory Skills: VLSI Physical Design Planning.
Experience: >10 YEARS.
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