Define DFT architecture and test strategy for complex SoCs, and own scan, MBIST, ATPG and pattern delivery from design through silicon bring-up.
What You Will Do
- Define DFT architecture and test strategy: scan, compression, MBIST/LBIST, JTAG/IJTAG, boundary scan.
- Plan and implement hierarchical DFT for full-chip and block-level designs.
- Own ATPG, fault-coverage targets, and pattern verification (zero-delay and SDF).
- Resolve DFT DRC and timing issues with RTL and PD teams.
- Deliver patterns to test engineering (STIL / WGL / Verilog) and support ATE bring-up and debug.
- Mentor DFT engineers; support yield analysis and silicon failure diagnosis.
What You Bring
- 15+ years in DFT with multiple SoC tape-outs and silicon bring-up.
- Expert in scan, ATPG, MBIST, at-speed test and hierarchical DFT methodologies.
- Hands-on with Synopsys (DFTMAX / TestMAX), Siemens Tessent or Cadence Modus flows.
- Strong with IEEE 1149.1, 1500 and 1687 standards.
- Working knowledge of STA, synthesis and ATE test flows.
- Scripting in Tcl, Python or Perl.
Positive to Have
- Multi-die / 3D test (IEEE 1838)
- Low-power test and automotive LBIST
- Silicon diagnosis and yield learning