At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. SOC/IP Verification Design Engineer

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases

PREFERRED EXPERIENCE:

Proficient in IP level ASIC verification with 7+years of experience
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Strong background in the C++ language, preferably on Linux with exposure to Windows platform




Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Positive working knowledge of SystemC and TLM with some related experience.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
Exposure to leadership or mentorship is an asset
Desirable assets with prior exposure to video codec system or other multimedia solutions.

ACADEMIC CREDENTIALS:

~ Bachelors or Masters degree in computer engineering/Electrical Engineering

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's 'Responsible AI Policy' is available here.

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