This is a outstanding opportunity to work as part of a highly regarded team to deliver leading-edge solutions.

Responsibilities
Testing the AMD/Xilinx FPGA software tools (Vivado, Vitis) end to end: write test plans and testcases for new tool features, run designs through the flow onto real boards, debug failures down to root cause and keep an automated regression suite healthy.

Skills
Must have

FPGA/ASIC design and verification flow

Verilog / SystemVerilog / VHDL and logic design

Debugging and root-cause analysis across software, IP and hardware

Test planning and testcase development

Scripting in Perl, TCL or C-shell

Building and maintaining regression automation

On-board (hardware) debugging

BE/MS in ECE

Experience: Level 1

entry level; strong academics asked for, no years stated.

Nice to have

Xilinx Vivado and Vitis

Xilinx FPGA architecture and tool flow

Protocols: SPI, I2C, PCIe, Ethernet, USB, HDMI

Interfaces: AXI, GT transceivers, DDR4, NoC

Other
Languages
English: B2 Upper Intermediate

Seniority
Junior

📌 Validation Officer (Planning) (Hyderabad)
🏢 Luxoft
📍 Hyderabad