Job Summary
JD for STA:
Experience: 5+ years
Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV
Analyze and resolve timing violations across hierarchical boundaries
Constraint Management
Define and validate SDC constraints for chip-level integration
Ensure proper timing budgeting and partitioning across blocks
Review and align block-level constraints with chip-level requirements
Signoff & Methodology
Lead signoff STA using tools like:
Synopsys PrimeTime
Cadence Tempus
Implement and improve:
MCMM (Multi-Corner Multi-Mode) flows
SI-aware analysis (crosstalk, noise)
ECO strategies for timing closure
Ensure timing correlation between block and top level
Debug & Optimization
Perform deep analysis on:
Critical paths
False/multicycle paths
Clock domain crossings (CDC timing perspective)
Drive timing ECOs with minimal impact on power/area
Strong expertise in:
STA fundamentals (setup/hold, skew, jitter, latency)
OCV/AOCV/POCV concepts
SI effects and derates
Hands-on experience with:
Synopsys PrimeTime / Cadence Tempus
Deep understanding of:
Clock tree design and analysis
Low power (UPF/CPF) impact on timing
Advanced nodes (7nm, 5nm preferred)
Experience in hierarchical STA flows
Exposure to automation (TCL/Python scripting)
Knowledge of EM/IR and physical effects on timing
Experience working with global teams / customers
Zero/near-zero timing violations at tapeout
Clean signoff across all modes/corners
Predictable timing closure cycles
Strong correlation between block and top-level timing
Key Responsibilities
JD for STA:
Experience: 5+ years
Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV
Analyze and resolve timing violations across hierarchical boundaries
Constraint Management
Define and validate SDC constraints for chip-level integration
Ensure proper timing budgeting and partitioning across blocks
Review and align block-level constraints with chip-level requirements
Signoff & Methodology
Lead signoff STA using tools like:
Synopsys PrimeTime
Cadence Tempus
Implement and improve:
MCMM (Multi-Corner Multi-Mode) flows
SI-aware analysis (crosstalk, noise)
ECO strategies for timing closure
Ensure timing correlation between block and top level
Debug & Optimization
Perform deep analysis on:
Critical paths
False/multicycle paths
Clock domain crossings (CDC timing perspective)
Drive timing ECOs with minimal impact on power/area
Strong expertise in:
STA fundamentals (setup/hold, skew, jitter, latency)
OCV/AOCV/POCV concepts
SI effects and derates
Hands-on experience with:
Synopsys PrimeTime / Cadence Tempus
Deep understanding of:
Clock tree design and analysis
Low power (UPF/CPF) impact on timing
Advanced nodes (7nm, 5nm preferred)
Experience in hierarchical STA flows
Exposure to automation (TCL/Python scripting)
Knowledge of EM/IR and physical effects on timing
Experience working with global teams / customers
Zero/near-zero timing violations at tapeout
Clean signoff across all modes/corners
Predictable timing closure cycles
Strong correlation between block and top-level timing
Skill Requirements
JD for STA:
Experience: 5+ years
Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV
Analyze and resolve timing violations across hierarchical boundaries
Constraint Management
Define and validate SDC constraints for chip-level integration
Ensure proper timing budgeting and partitioning across blocks
Review and align block-level constraints with chip-level requirements
Signoff & Methodology
Lead signoff STA using tools like:
Synopsys PrimeTime
Cadence Tempus
Implement and improve:
MCMM (Multi-Corner Multi-Mode) flows
SI-aware analysis (crosstalk, noise)
ECO strategies for timing closure
Ensure timing correlation between block and top level
Debug & Optimization
Perform deep analysis on:
Critical paths
False/multicycle paths
Clock domain crossings (CDC timing perspective)
Drive timing ECOs with minimal impact on power/area
Strong expertise in:
STA fundamentals (setup/hold, skew, jitter, latency)
OCV/AOCV/POCV concepts
SI effects and derates
Hands-on experience with:
Synopsys PrimeTime / Cadence Tempus
Deep understanding of:
Clock tree design and analysis
Low power (UPF/CPF) impact on timing
Advanced nodes (7nm, 5nm preferred)
Experience in hierarchical STA flows
Exposure to automation (TCL/Python scripting)
Knowledge of EM/IR and physical effects on timing
Experience working with global teams / customers
Zero/near-zero timing violations at tapeout
Clean signoff across all modes/corners
Predictable timing closure cycles
Strong correlation between block and top-level timing
Must Have Skill
Physical Design
Good to Have Skill
Other Requirements
JD for STA:
Experience: 5+ years
Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV
Analyze and resolve timing violations across hierarchical boundaries
Constraint Management
Define and validate SDC constraints for chip-level integration
Ensure proper timing budgeting and partitioning across blocks
Review and align block-level constraints with chip-level requirements
Signoff & Methodology
Lead signoff STA using tools like:
Synopsys PrimeTime
Cadence Tempus
Implement and improve:
MCMM (Multi-Corner Multi-Mode) flows
SI-aware analysis (crosstalk, noise)
ECO strategies for timing closure
Ensure timing correlation between block and top level
Debug & Optimization
Perform deep analysis on:
Critical paths
False/multicycle paths
Clock domain crossings (CDC timing perspective)
Drive timing ECOs with minimal impact on power/area
Strong expertise in:
STA fundamentals (setup/hold, skew, jitter, latency)
OCV/AOCV/POCV concepts
SI effects and derates
Hands-on experience with:
Synopsys PrimeTime / Cadence Tempus
Deep understanding of:
Clock tree design and analysis
Low power (UPF/CPF) impact on timing
Advanced nodes (7nm, 5nm preferred)
Experience in hierarchical STA flows
Exposure to automation (TCL/Python scripting)
Knowledge of EM/IR and physical effects on timing
Experience working with global teams / customers
Zero/near-zero timing violations at tapeout
Clean signoff across all modes/corners
Predictable timing closure cycles
Robust correlation between block and top-level timing
📌 Senior Design Lead (India)
🏢 HCLTech
📍 India