Job Summary

Experience: 5+ years
Experience with Vectorless Low Power (VCLP/CLP) tools is a must
Enable and execute UPF-based low-power verification at block and full-chip levels
Validate power intent correctness including isolation, retention, level shifters, power switches, and always-on logic
Debug and resolve low-power violations related to missing/incorrect UPF definitions and design connectivity
Create reference low-power flows and testcases to evaluate tools, PDKs, and EM/LP-related collateral
Develop and automate VCLP workflows to enhance accuracy and reduce runtime of VCLP signoff. Automation using Python/Perl/Tcl is preferred
Collaborate with RTL, PD, and Power Architecture teams to close low-power issues
Prepare low-power signoff reports and maintain VCLP checklists
Document VCLP methodologies and train users on low-power best practices

Key Responsibilities

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Skill Requirements

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Must Have Skill

Physical Design

Valuable to Have Skill

Other Requirements

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📌 Technical Architect (India)
🏢 HCLTech
📍 India