Min 10+ years in DFT (Proven experience in: Chip-Level DFT Ownership)
Role Overview
Lead and own chip-level DFT architecture, implementation, and signoff for complex SoCs. Responsible for ensuring high test coverage, manufacturability, and test cost optimization, while driving seamless integration across IPs and subsystems.
Key Responsibilities
DFT Ownership
Own end-to-end chip-level DFT strategy and execution
Define DFT architecture for full chip including scan, MBIST, LBIST, and boundary scan
Ensure DFT readiness from RTL to tape out.
DFT Architecture & Planning
Architect and implement:
Scan insertion and compression (EDT)
MBIST (Memory BIST)
LBIST (Logic BIST)
JTAG / Boundary Scan (IEEE 1149.x)
Define test modes, test clocks, and test access mechanisms (TAM)
Plan and manage test IO requirements and pin mixing.
Implementation & Integration
Drive DFT insertion and integration at chip level
Ensure proper integration of:
Third-party IP DFT requirements
Block-level DFT into top-level environment
Work closely with RTL and PD teams for clean implementation
ATP G & Coverage Closure
Own ATPG pattern generation and debug
Achieve high:
Stuck-at coverage
Transition fault coverage
Analyze and close:
Coverage gaps
Untestable faults
Optimize for pattern count and test time
Physical & Timing Awareness
Ensure DFT is:
Timing clean (no test mode violations)
Physically feasible (routing, congestion aware)
Work with STA and PD teams for:
Scan timing closure
Test mode timing validation
Post-Silicon & Manufacturing Support
Support:
Silicon bring-up
ATE debug and yield analysis
Work with test engineers for:
Pattern bring-up
Yield improvement
Cross-Functional Collaboration
Interface with:
RTL / Design teams
Physical Design (PD)
STA team
Validation and ATE teams
Ensure alignment across design, test, and manufacturing
Leadership
Lead and mentor DFT engineers
Drive DFT reviews, checklists, and signoff criteria
Act as final owner for DFT quality and signoff
Required Skills & Expertise
Technical
Robust expertise in:
Scan architecture and compression techniques ATPG and fault modeling MBIST/LBIST design and integration
Deep understanding of:
DFT timing challenges
Low-power impact on test (UPF/CPF awareness)
Tools
Hands-on experience with:
Synopsys DFT Compiler / TetraMAX / TestMAX, Cadence Modus
Familiarity with:
STA tools (PrimeTime) for test timing validation
Multiple successful tapeouts
Soft Skills
Strong debugging and analytical thinking
Ability to lead cross-functional teams
Good communication with stakeholders and customers
Good to Have
Experience with:
Low-power DFT techniques
Hierarchical DFT flows
Automotive / safety (ISO 26262) test requirements
Scripting:
TCL / Python for automation
Success Metrics
High fault coverage (stuck-at, transition)
Optimized pattern count and test time
Smooth silicon bring-up and minimal test escapes
High manufacturing yield
Clean DFT signoff at tape out.
Interested Engineers ping me or send invitation to connect further.