Job Purpose We are seeking an experienced FPGA Design and Validation Engineer to own the end-to-end flow from RTL adaptation to physical board-level validation. You will optimize architecture for Xilinx hardware, resolve complex timing issues, and lead bench-level electrical debug.
Key Responsibilities
• FPGA Flow & Implementation: Manage the complete RTL-to-bitfile flow, including synthesis, place-and-route, and bitfile generation.
• ASIC RTL Adaptation: Modify and map existing ASIC RTL blocks to fit and perform optimally on Xilinx target FPGAs.
• Timing & Constraints: Develop timing constraints and analyze reports to resolve clock domain crossings (CDC) and loops.
• Test & Automation:
Write C-based test cases for FPGA verification and develop Python scripts for automated testing.
• Hardware Validation: Perform bench-level electrical validation and board debug using high-speed oscilloscopes and digital analyzers. Technical Skills Required
• Languages: VHDL, Verilog, SystemVerilog, Embedded C, Python
• Tools: Xilinx Vivado, Synplify Synthesis, SVN/Git
• Lab Equipment: Oscilloscopes, Logic Analyzers, JTAG debuggers Qualifications
•
Education:
B.
E / B.
Tech / M.
Tech in ECE, EEE, or VLSI.
• 8+ years of core experience in FPGA design and physical board bring-up.