Position: Analog Design Engineer (ASIC) (CE810SI RM 4592) Functional Area: Analog Mixed signal Design Work Mode : Work from Office Experience Level : 8-10 Relevant Experience required : 8 – 10 Education Required: BTech (MTech will be additional and positive) Must Have Skills
• Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc
• Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
• Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
• Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus. Good to have

skills:
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📌 Analog Design Engineer (Bengaluru)
🏢 Source right
📍 Bengaluru