Experience:
4 12 years. ### Job Summary Prove the RTL is right UVM testbenches, coverage and formal before it reaches silicon. ### Job Details
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Job type
Full time
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Experience:
4 12 years
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Location:
Bengaluru, India ### Responsibilities
- Build UVM testbenches and constrained-random environments for blocks and SoCs.
- Define verification and coverage plans; close functional and code coverage.
- Apply formal where it pays, and hunt the escapes simulation nearly misses. ### Skills
- UVM
- SystemVerilog
- Coverage
- Formal
- Assertions
- Verification Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.