DV Architect
15+ Years
The Role

Define verification strategy and architect scalable UVM environments for subsystem and SoC designs, owning coverage closure and verification signoff.

What You Will Do

- Define the end-to-end verification strategy, plans, coverage models and signoff criteria.
- Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level.
- Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification.
- Establish regression, automation and quality metrics infrastructure.
- Lead technical reviews of test plans, testbench architecture and coverage closure.
- Work with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

What You Bring

- 15+ years in ASIC/SoC verification, with ownership of subsystem and chip-level verification through tape-out.
- Expert SystemVerilog, UVM,



SVA and coverage-driven verification.
- Experience leading DV teams and being the technical escalation point.
- Solid with high-speed and bus protocols such as PCIe, DDR/LPDDR, Ethernet, AMBA, UCIe.
- Hands-on with regression management, debug and gate-level / power-aware simulation.
- Scripting in Python, Perl or Shell.

Good to Have

- Formal verification and emulation / FPGA prototyping
- Hardware/software co-verification
- Post-silicon bring-up exposure

This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DV Architect (Chennai)
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