Job Title: Design Verification Engineer Low Power

Experience: 5+ Years
Location: Bangalore

Job Description:

- Own verification of subsystem and SoC-level designs using SystemVerilog and UVM.
- Develop and enhance UVM testbenches for current features and design changes.
- Perform low-power verification using UPF, including power gating, retention, isolation, and wake-up scenarios.
- Execute Formal Verification at block and SoC levels.
- Perform FPV, Formal Connectivity, UNR analysis, SVA, and coverage closure.
- Debug issues and drive verification signoff in collaboration with design, architecture, and power teams.

Required Skills:

- Strong experience in SystemVerilog and UVM.
- Hands-on experience in Low Power Verification and UPF.
- Expertise in JasperGold / VC Formal.
- Experience in FPV, Formal Connectivity, UNR, SVA, and Coverage Closure.
- Knowledge of power-aware simulation, retention, isolation, and clock/power gating.
- Strong debugging and technical leadership skills.

For More Info Pls Contact on (phone hidden) / [email protected]

📌 Design Verification Engineer - Low Power (Bengaluru)
🏢 Trigent Software
📍 Bengaluru