Company :Qualcomm India Private Limited

Job Area :Engineering Group, Engineering Group > Hardware Engineering

General Summary : Job Area: Engineering - IP Design / Hardware Security

Location: Bangalore

About the Role : We are looking for an experienced Security RTL Design Engineer to join the Hardware Security team and own RTL design for secure hardware IPs and subsystems used in next-generation SoCs. The role focuses on cryptographic accelerators, Root of Trust, secure enclaves, key management, secure boot, access control, and other security-critical design blocks.

The engineer will drive the complete front-end RTL development cycle, from micro-architecture definition and SystemVerilog implementation through quality checks, synthesis readiness, full-chip integration support, and tape-out closure. The role requires strong ASIC design fundamentals and practical understanding of security threats such as side-channel leakage, fault injection, unauthorized debug access, and key exposure.

Responsibilities :

- Lead micro-architecture definition and RTL design ownership for hardware security modules, cryptographic engines, and security subsystems.
- Translate architecture requirements, software use cases, threat-model inputs, and interface specifications into clean, implementation-ready micro-architecture specifications.
- Implement high-quality SystemVerilog RTL for blocks such as AES, SHA, ECC/RSA accelerators, TRNG, key management, secure boot logic, access-control logic, and anti-tamper features.
- Incorporate secure design techniques, including side-channel mitigation, fault-injection resistance, secure state-machine design, zeroization, privilege checks, and debug lockdown mechanisms.
- Collaborate with architecture, verification, physical design, DFT, firmware, software,



and SoC integration teams to meet security, performance, area, power, and schedule goals.
- Qualify RTL through front-end design checks such as lint, clock-domain crossing, reset-domain crossing, synthesis, DFT, low-power, formal, and equivalence-readiness reviews.
- Support performance, latency, bandwidth, buffer sizing, and configuration tuning for security IPs and related system interfaces.
- Participate in full-chip integration, emulation, silicon bring-up, post-silicon debug, and validation of hardware security features.
- Contribute to threat-model reviews, security design reviews, standards alignment, and certification-readiness activities where applicable.
- Mentor junior engineers and improve RTL design methodology, design review quality, reusable collateral, and secure-by-construction design practices.

Required Skillset :

- Strong VLSI logic design expertise with deep ownership of complex SoC or IP-level RTL design.
- Hands-on experience in SystemVerilog/Verilog RTL coding, micro-architecture, front-end ASIC design flow, and design convergence.
- Practical hardware security design experience in cryptographic hardware, Root of Trust, secure enclaves, secure processors, key management, or equivalent security IP.
- Strong understanding of cryptographic acceleration and secure datapath/control design, including AES, SHA, RSA/ECC, TRNG, secure boot, and lifecycle-controlled access paths.




- Valuable understanding of side-channel and fault attack countermeasures, secure state machines, privilege separation, tamper resistance, and physical security techniques.
- Working knowledge of on-chip interconnect and register-access protocols such as APB, AHB, AXI, ACE, or ACE-Lite.
- Good understanding of clock/reset domains, clock gating, low-power intent, debug infrastructure, and SoC integration constraints.
- Experience with ASIC convergence activities such as synthesis, static timing analysis, lint, CDC/RDC, DFT, low-power checks, formal verification, and LEC.
- Strong debugging, analytical thinking, problem solving, communication, and cross-site collaboration skills.

Desired Skillset :

- Experience with security certifications or standards such as FIPS, Common Criteria, or equivalent product security review processes.
- Experience with automotive, mobile, edge AI, server, or high-assurance security solutions.
- Knowledge of RISC-V or Arm secure processors, Trusted Execution Environments, secure monitor flows, or secure enclave architectures.
- Experience with advanced process nodes such as 7 nm and below, including physical design interaction and timing/power closure trade-offs.
- Experience in designs optimized for low power, including dynamic clock gating, memory retention, memory power collapse, and logic power collapse.
- Proficiency in Python, Tcl, Perl, C, C++, or SystemC for automation, debug utilities, performance models, or design collateral generation.
- Working knowledge of functional coverage, assertions, formal property checks, and security-oriented verification planning.

Minimum Qualifications :

- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related

📌 Security Rtl Design Engineer(Smmu) - sr Engineer (Bengaluru)
🏢 Qualcomm
📍 Bengaluru