At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. SENIOR MANAGER SILICON DESIGN ENGINEER
Sr Manager of ASIC RTL Design Verification is to lead the pre-silicon functional verification organization.
The role requires deep technical expertise in c/c++/ASM SystemVerilog/UVM-based verification, strong understanding of digital RTL and SoC architectures, and demonstrated experience building and leading high-performing verification teams.
He will work closely with RTL design, architecture, and program management teams to deliver high-quality, functionally correct RTL and achieve predictable tape-out schedules.

Drive verification planning and execution at full-chip SoC levels.
Drive verification quality, predictability, efficiency, and reuse across semiconductor programs.

Provide technical leadership for C/C++/ASM/SystemVerilog/UVM-based constrained-random verification .
Mentor senior engineers and develop future technical and management leaders.

RTL Design
IP Design and Verification teams
CAD/EDA Infrastructure
Program Management
Firmware/Software teams where required for RTL verification
Drive alignment on specifications, verification requirements, dependencies, schedules, quality metrics, and RTL sign-off criteria.

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.

- 17+ years of ASIC/SoC RTL verification experience ,



with significant technical and people leadership responsibility.
- Proven track record leading verification of complex semiconductor products through RTL sign-off and tape-out.
- Strong understanding of clock/reset architectures, interrupts, register interfaces, memory interfaces, and power-management functionality from an RTL verification perspective.
- Demonstrated ability to lead verification across multiple projects and geographically distributed teams.
- Strong engineering judgment and ability to make data-driven RTL sign-off decisions.
- Experience verifying multi-core or multi-engine SoCs with complex interconnect and memory architectures.

Experience with protocols such as PCIe, CXL, Ethernet, DDR/LPDDR, USB, or other high-speed interfaces relevant to the product.
Experience with X86 and ARM processor subsystems.
Experience in ARM based and X86 based SOC.
Experience developing reusable UVM verification IP and environments.
Experience with low-power RTL verification, including UPF-driven simulation where applicable.
Robust scripting and automation experience using Python or similar languages.
Experience establishing verification methodologies and infrastructure across multiple semiconductor product generations.
#AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's 'Responsible AI Policy' is available

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