Job Responsibilities Coding of testcase for SoC using SystemVerilog (UVM) & C SoC Level verification is a must. AMBA bus protocol like AHB, AXI is a must. Generate Verification Plan from the Specifications using vManager. Determine Coverage and design completeness requirements. Generate random-constraint tests to meet coverage requirements. Create Assertions, cover-groups, checkers, monitors and automatic reporting. Set-up and run regression, analyze/debug the failure and file JIRA. Job Requirements BSEE (MSEE pref.) or equivalent with 5 to 9 years skilled industry experience in Digital multi core SoC verification. Experience in digital Verification. AUTOMOTIVE SOC is plus IP like Ether CAT, CAN, LIN and MRAM and so on. UVM testbench creation, writing and implementation is a plus. Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus Must be able to work independently with limited supervision and work closely with team.