As a Senior EMIR Engineer, you will specialize in power integrity, rail analysis, and electromigration verification to ensure long-term reliability and performance of complex silicon designs.
Education Requirements
Degree: B.E. / B.Tech / M.E. / M.Tech in Electrical Engineering, Electronics Engineering, Microelectronics, or VLSI Systems.
Key Responsibilities
Execute static and agile IR drop analysis, vector-based and vectorless EMIR runs at block and full-chip levels.
Perform Signal Electromigration (Signal EM) and Power Grid Electromigration (Power EM) evaluations.
Identify power grid bottlenecks, weak power structures, and local voltage drop issues; propose structural ECOs to PD teams.
Develop power analysis flows for energetic activity scenarios using VCD/FSDB files.
Guide design teams on power network architecture, decap placement, and bump patterns.
Technical Qualifications
Experience: 5+ years dedicated to Power Integrity and EMIR analysis for deep sub-micron designs.
Tools: High proficiency in Ansys RedHawk / RedHawk-SC, Cadence Voltus, or Synopsys PrimeRail.
Nodes: Experience handling sub-7nm power grid integrity challenges (FinFET / GAAFET architectures).
Skills: Solid understanding of power grid synthesis, package/on-die RLC networks, thermal effects, and vector-driven energetic IR debug.
Scripting: Proficient in TCL, Python, or Perl to build automated analysis and reporting pipelines.