What you'll do
Own the design and implementation of functional blocks within the accelerator pipeline
Write and debug RTL (Verilog/SystemVerilog) for your assigned block
Collaborate with verification engineers to define test plans and close coverage
Analyze performance, timing, and area tradeoffs and propose improvements
Participate in design reviews and document your block's architecture and behavior

What we're looking for
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
Recently completed coursework in computer microarchitecture, covering at least one of:
Cache/memory systems
Computer arithmetic
Pipeline design
Working knowledge of a contemporary ISA
Familiarity with parallel accelerator architectures, such as:
SIMD / SIMT / vector processing
Out-of-order scheduling
Hands-on Verilog/SystemVerilog experience, including:
Simulation and testbench debugging




Timing and power closure
Understanding of the end-to-end ASIC design flow and general VLSI concepts
Scripting experience (Python, Perl, or Tcl); C/C++ a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Advantages: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D;, 401(k)

📌 Ai Accelerator Rtl Microarchitecture/design Engineer Full Time Kolkata Metropolitan Area
🏢 RosaicLabs
📍 Kolkata Metropolitan Area